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hot swappable dual i 2 c isolators adum1250/ADUM1251 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features bidirectional i 2 c communication open-drain interfaces suitable for hot swap applications 30 ma current sink capability 1000 khz operation 3.0 v to 5.5 v supply/logic levels 8-lead soic lead-free package high temperature operation: 105c safety and regulatory approvals ul recognition 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a (pending) vde certificate of conformity (pending) din en 60747-5-2 (vde 0884 part 2): 2003-01 din en 60950 (vde 0805): 2001-12; din en 60950: 2000 v iorm = 560 v peak applications isolated i 2 c, smbus, or pmbus interfaces multilevel i 2 c interfaces power supplies networking power-over-ethernet functional block diagrams encode decode decode encode encode decode decode encode v dd1 sda 1 scl 1 gnd 1 v dd2 sda 2 scl 2 gnd 2 1 2 3 4 8 7 6 5 06401-001 figure 1. adum1250 functional block diagram encode decode encode decode decode encode v dd1 sda 1 scl 1 gnd 1 v dd2 sda 2 scl 2 gnd 2 1 2 3 4 8 7 6 5 06401-002 figure 2. ADUM1251 functional block diagram general description the adum1250/ADUM1251 1 are hot swappable digital isolators with non latching bidirectional communication channels compatible with i 2 c interfaces. this eliminates the need for splitting i 2 c signals into separate transmit and receive signals for use with standalone optocouplers. the adum1250 provides two bidirectional channels supporting a complete isolated i 2 c interface. the ADUM1251 provides one bidirectional channel and one unidirectional channel for those applications where a bidirectional clock is not required. both the adum1250 and ADUM1251 contain hot swap circuitry to prevent glitching data when an unpowered card is inserted onto an active bus. these isolators are based on i coupler? chip scale transformer technology from analog devices, inc. i coupler is a magnetic isolation technology with functional, performance, size, and power consumption advantages as compared to optocouplers. with the adum1250/ADUM1251, i coupler channels can be integrated with semiconductor circuitry, which enables a complete isolated i 2 c interface to be provided in a small form factor. 1 protected by u.s. patents 5,952,849 and 6,873,065. other patents pending. rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved.
adum1250/ADUM1251 rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagrams ............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 package characteristics ............................................................... 5 regulatory information ............................................................... 5 insulation and safety-related specifications ............................ 5 din en 60747-5-2 (vde 0884 part 2) insulation characteristics .............................................................................. 6 recommended operating conditions ...................................... 6 absolute maximum ratings ............................................................7 esd caution ...................................................................................7 pin configuration and function descriptions ..............................8 test conditions ..................................................................................9 application notes ........................................................................... 10 functional description .............................................................. 10 startup .......................................................................................... 10 typical application diagram .................................................... 11 magnetic field immunity ............................................................. 11 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 12 revision history 10/06revision 0: initial version 0
adum1250/ADUM1251 rev. 0 | page 3 of 12 specifications electrical characteristics dc specifications all voltages are relative to their respective ground. all min/max specifications apply over the entire recommended operating ra nge, unless otherwise noted. all typical specifications are at t a = 25c, v dd1 = 5 v, and v dd2 = 5 v, unless otherwise noted. table 1. parameter symbol min typ max unit test conditions adum1250 input supply current, side 1, 5 v i dd1 2.8 5.0 ma v dd1 = 5 v input supply current, side 2, 5 v i dd2 2.7 5.0 ma v dd2 = 5 v input supply current, side 1, 3.3 v i dd1 1.9 3.0 ma v dd1 = 3.3 v input supply current, side 2, 3.3 v i dd2 1.7 3.0 ma v dd2 = 3.3 v ADUM1251 input supply current, side 1, 5 v i dd1 2.8 6.0 ma v dd1 = 5 v input supply current, side 2, 5 v i dd2 2.5 4.7 ma v dd2 = 5 v input supply current, side 1, 3.3 v i dd1 1.8 3.0 ma v dd1 = 3.3 v input supply current, side 2, 3.3v i dd2 1.6 2.8 ma v dd2 = 3.3 v leakage currents i sda1 , i sda2 , i scl1 , i scl2 0.01 10 a v sda1 = v dd1 , v sda2 = v dd2 , v scl1 = v dd1 , v scl2 = v dd2 side 1 logic levels logic input threshold 1 v sda1t , v scl1t 500 700 mv logic low output voltages v sda1ol , v scl1ol 600 900 mv i sda1 = i scl1 = 3.0 ma 600 850 mv i sda1 = i scl1 = 0.5 ma input/output logic low level difference 2 v sda1 , v scl1 50 mv side 2 logic levels logic low input voltage v sda2il , v scl2il 0.3 v dd2 v logic high input voltage v sda2ih , v scl2ih 0.7 v dd2 v logic low output voltage v sda2ol , v scl2ol 400 mv i sda2 = i scl2 = 30 ma 1 v < 0.5 v, v > 0.7 v. il ih 2 v = v C v . this is the minimum difference between the output logic low level and the input logic threshold within a given component. thi s ensures that there is no possibility of the part latching up the bus to which it is connected. s1 s1ol s1t
adum1250/ADUM1251 rev. 0 | page 4 of 12 ac specifications all voltages are relative to their respective ground. all min/max specifications apply over the entire recommended operating ra nge, unless otherwise noted. all typical specifications are at t a = 25c, v dd1 = 5 v, and v dd2 = 5 v, unless otherwise noted. refer to figure 5 . table 2. parameter symbol min typ max unit test conditions maximum frequency 1000 khz output fall time 5 v operation 4.5 v v dd1 ,v dd2 5.5 v, c l1 = 40 pf, r1 = 1.6 k, c l2 = 400 pf, r2 = 180 side 1 output (0.9 v dd1 to 0.9 v) t f1 13 26 120 ns side 2 output (0.9 v dd2 to 0.1 v dd2 ) t f2 32 52 120 ns 3 v operation 3.0 v v dd1 ,v dd2 3.6 v, c l1 = 40 pf, r1 = 1.0 k, c l2 = 400 pf, r2 = 120 side 1 output (0.9 v dd1 to 0.9 v) t f1 13 32 120 ns side 2 output (0.9 v dd2 to 0.1 v dd2 ) t f2 32 61 120 ns propagation delay 5 v operation 4.5 v dd1 , v dd2 5.5 v, c l1 = c l2 = 0, r1 = 1.6 k, r2 = 180 side 1-to-side 2, rising edge 1 t plh12 95 130 ns side 1-to-side 2, falling edge 2 t phl12 162 275 ns side 2-to-side 1, rising edge 3 t plh21 31 70 ns side 2-to-side 1, falling edge 4 t phl21 85 155 ns 3 v operation 3.0 v v dd1 ,v dd2 3.6 v, c l1 = c l2 = 0, r1 = 1.0 k, r2 = 120 side 1-to-side 2, rising edge 1 t plh12 82 125 ns side 1-to-side 2, falling edge 2 t phl12 196 340 ns side 2-to-side 1, rising edge 3 t plh21 32 75 ns side 2-to-side 1, falling edge 4 t phl21 110 210 ns pulse width distortion 5 v operation 4.5 v v dd1 , v dd2 5.5 v, c l1 = c l2 = 0, r1 = 1.6 k, r2 = 180 side 1-to-side 2, |t plh12 ? t phl12 | pwd 12 67 145 ns side 2-to-side 1, |t plh21 ? t phl21 | pwd 21 54 85 ns 3 v operation 3.0 v v dd1 ,v dd2 3.6 v, c l1 = c l2 = 0, r1 = 1.0 k, r2 = 120 side 1-to-side 2, |t plh12 ? t phl12 | pwd 12 114 215 ns side 2-to-side 1, |t plh21 ? t phl21 | pwd 21 77 135 ns common-mode transient immunity 5 |cm h |, |cm l | 25 35 kv/s 1 t plh12 propagation delay is measured from the side 1 input logic threshold to an output value of 0.7 v dd2 . 2 t phl12 propagation delay is measured from the side 1 input logic threshold to an output value of 0.4 v. 3 t plh21 propagation delay is measured from the side 2 input logic threshold to an output value of 0.7 v dd1 . 4 t plh21 propagation delay is measured from the side 2 input logic threshold to an output value of 0.9 v. 5 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed.
adum1250/ADUM1251 rev. 0 | page 5 of 12 package characteristics table 3. parameter symbol min typ max unit test conditions resistance (input-output) 1 r i-o 10 12 capacitance (input-output) 1 c i-o 1.0 pf f = 1 mhz input capacitance c i 4.0 pf ic junction-to-case thermal resistance, side 1 jci 46 c/w thermocouple located at center of package underside ic junction-to-case thermal resistance, side 2 jco 41 c/w 1 the device is considered a 2-terminal device; pin 1 through pin 4 are shorted together, and pin 5 through pin 8 are shorted to gether. regulatory information the adum1250/ADUM1251 has been approved by the following organizations: table 4. ul csa (pending) vde (pending) recognized under 1577 component recognition program 1 basic insulation, 2500 v rms isolation rating approved under csa component acceptance notice #5a basic insulation per csa 60950-1-03 and iec 60950-1, 400 v rms (560 v peak) maximum working voltage certified according to din en 60747-5-2 (vde 0884 part 2):2003-01 2 basic insulation,400 v rms (560 v peak) maximum working voltage file e214100 file 205078 file 2471900-4880-0001 1 in accordance with ul1577, each device is proof tested by applying an insulation test voltage 3000 v rms for 1 second (current leakage detect ion limit = 5 a). 2 in accordance with din en 60747- 5-2, each device is proof test ed by applying an in sulation test voltage 1050 v peak for 1 se cond (partial discharge detection limit = 5 pc). insulation and safety-related specifications table 5. parameter symbol value unit conditions rated dielectric insulation voltage 2500 v rms 1 minute duration minimum external air gap (clearance) l(i01) 4.90 min mm measured from input termin als to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 4.01 min mm measured from input termin als to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1)
adum1250/ADUM1251 rev. 0 | page 6 of 12 din en 60747-5-2 (vde 0884 part 2) insulation characteristics this isolator is suitable for basic isolation only within the safety limit data. maintenance of the safety data is ensured by p rotective circuits. the * marking on the package denotes din en 60747-5-2 approval for a 560 v peak working voltage. table 6. description symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree (din vde 0110, table 1) 2 maximum working insulation voltage v iorm 560 v peak input-to-output test voltage, method b1 v pr 1050 v peak v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc input-to-output test voltage, method a v pr after environmental tests subgroup 1 v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc 896 v peak after input and/or safety test subgroup 2/3 672 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc highest allowable overvoltag e (transient overvoltage, t tr = 10 sec) v tr 4000 v peak safety-limiting values (maximum value allo wed in the event of a failure (see also figure 3 ) case temperature t s 150 c side 1 current i s1 160 ma side 2 current i s2 170 ma insulation resistance at t s , v io = 500 v r s >10 9 case temperature (c) safety-limiting current (ma) 0 0 350 50 100 150 200 50 300 06401-003 150 100 200 250 figure 3. thermal derating curve, dependence of safety limiting values on case temperature, per din en 60747-5-2 recommended operat ing conditions table 7. parameter symbol min max unit operating temperature t a ?40 +105 c supply voltages 1 v dd1 , v dd2 3.0 5.5 v input/output signal voltage v sda1 , v scl1 , v sda2 , v scl2 5.5 v capacitive load, side 1 c l1 40 pf capacitive load, side 2 c l2 400 pf static output loading, side 1 i sda1 , i scl1 0.5 3 ma static output loading, side 2 i sda2 , i scl2 0.5 30 ma 1 all voltages are relative to their respective ground. see the application notes section for data on immunity to external magnetic fields.
adum1250/ADUM1251 rev. 0 | page 7 of 12 absolute maximum ratings ambient temperature = 25c, unless otherwise noted. table 8. parameter symbol min max unit storage temperature t st ?55 +150 c ambient operating temperature t a ?40 +105 c supply voltages 1 v dd1 , v dd2 ?0.5 +7.0 v input/output voltage 1 , side 1 v sda1 , v scl1 ?0.5 v dd1 + 0.5 v input/output voltage 1 , side 2 v sda2 , v scl2 ?0.5 v dd2 + 0.5 v average output current, per pin2 i o ma common-mode transients 3 ?100 +100 kv/s 1 all voltages are relative to their respective ground. 2 see figure 3 for maximum rated current values for various temperatures. 3 refers to common-mode transients across the insulation barrier. common- mode transients exceeding the abso lute maximum rating may cause latch- up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adum1250/ADUM1251 rev. 0 | page 8 of 12 pin configuration and fu nction descriptions v dd1 1 sda 1 2 scl 1 3 gnd 1 4 v dd2 8 sda 2 7 scl 2 6 gnd 2 5 adum1250/ ADUM1251 top view (not to scale) 06401-004 figure 4. adum1250/ADUM1251 pin configuration table 9. adum1250 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage, 3.0 v to 5.5 v. 2 sda 1 data input/output, side 1. 3 scl 1 clock input/output, side 1. 4 gnd 1 ground 1. ground reference for isolator side 1. 5 gnd 2 ground 2. isolated ground reference for isolator side 2. 6 scl 2 clock input/output, side 2. 7 sda 2 data input/output, side 2. 8 v dd2 supply voltage, 3.0 v to 5.5 v. table 10. ADUM1251 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage, 3.0 v to 5.5 v. 2 sda 1 data input/output, side 1. 3 scl 1 clock input, side 1. 4 gnd 1 ground 1. ground reference for isolator side 1. 5 gnd 2 ground 2. isolated ground reference for isolator side 2. 6 scl 2 clock output, side 2. 7 sda 2 data input/output, side 2. 8 v dd2 supply voltage, 3.0 v to 5.5 v.
adum1250/ADUM1251 rev. 0 | page 9 of 12 test conditions encode decode decode encode encode decode decode encode v dd1 sda 1 scl 1 v dd2 sda 2 scl 2 c l2 gnd 2 1 2 3 8 7 6 0 6401-005 5 gnd 1 4 c l2 r2 r2 c l1 c l1 r1 r1 figure 5. timing test diagram
adum1250/ADUM1251 rev. 0 | page 10 of 12 application notes functional description the adum1250/ADUM1251 interfaces on each side to a bidirectional i 2 c signal. internally, the i 2 c interface is split into two unidirectional channels communicating in opposing directions via a dedicated i coupler isolation channel for each. one channel (the bottom channel of each channel pair shown in figure 6 ) senses the voltage state of the side 1 i 2 c pin and transmits its state to its respective side 2 i 2 c pin. both the side 1 and the side 2 i 2 c pins are designed to interface to an i 2 c bus operating in the 3.0 v to 5.5 v range. a logic low on either causes the opposite pin to be pulled low enough to comply with the logic low threshold requirements of other i 2 c devices on the bus. avoidance of i 2 c bus contention is ensured by an input low threshold at sda 1 or scl 1 guaranteed to be at least 50 mv less than the output low signal at the same pin. this prevents an output logic low at side 1 being transmitted back to side 2 and pulling down the i 2 c bus. since the side 2 logic levels/thresholds are standard i 2 c values, multiple adum1250/ADUM1251 devices connected to a bus by their side 2 pins can communicate with each other and with other devices having i 2 c compatibility 1 . however, since the side 1 pin has a modified output level/input threshold, this side of the adum1250/ADUM1251 can only communicate with devices conforming to the i 2 c standard. in other words, side 2 of the adum1250/ADUM1251 is i 2 c- compliant while side 1 is only i 2 c-compatible. the output logic low levels are independent of the v dd1 and v dd2 voltages. the input logic low threshold at side 1 is also independent of v dd1 . however, the input logic low threshold at side 2 is designed to be at 0.3 v dd2 , consistent with i 2 c requirements. the side 1 and side 2 pins have open-collector outputs whose high levels are set via pull-up resistors to their respective supply voltages. encode decode decode encode encode decode decode encode v dd1 sda 1 scl 1 v dd2 sda 2 scl 2 c l gnd 2 1 2 3 8 7 6 0 6401-006 5 gnd 1 4 c l r2 r2 figure 6. adum1250 block diagram 1 here a distinction is made between i 2 c compatibility and i 2 c compliance. i 2 c compatibility refers to situations in which a component's logic levels do not necessarily meet the requirements of the i 2 c specification but still allow the component to communication with an i 2 c-compliant device. i 2 c compliance refers to situations in which a component's logic levels meet the requirements of the i 2 c specification. startup both the v dd1 and v dd2 supplies have an under voltage lockout feature to prevent the signal channels from operating unless certain criteria are met. this avoids the possibility of input logic low signals from pulling down the i 2 c bus inadvertently during power-up/power-down. the two criteria that must be met in order for the signal channels to be enabled are as follows: ? both supplies must be at least 2.5 v. ? at least 40 s must elapse after both supplies exceeded the internal startup threshold of 2.0 v. until both of these criteria are met for both supplies, the adum1250/ADUM1251 outputs are pulled high, ensuring a startup that avoids any disturbances on the bus. figure 7 and figure 8 illustrate the supply conditions for fast and slow input supply slew rates. 06401-007 minimum recommended operating supply, 3.0v minimum valid supply, 2.5v internal startup threshold, 2.0v 40s supply valid figure 7. start-up condition, supply slew rate >12.5 v/ms 06401-008 40s supply valid min. recommended operating supply, 3.0v min. valid supply, 2.5v internal startup threshold, 2.0v figure 8. start-up condition, supply slew rate <12.5 v/ms
adum1250/ADUM1251 rev. 0 | page 11 of 12 typical application diagram 06401-009 v dd g nd 1 sda 1 gnd 2 v 2 sda 2 adum1250 scl 1 scl 2 i 2 c bus 1 2 3 4 8 7 6 5 figure 9. typical isolated i 2 c interface using adum1250 magnetic field immunity the adum1250 is extremely immune to external magnetic fields. the limitation on the adum1250s magnetic field immunity is set by the condition in which induced voltage in the transformers receiving coil is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which this may occur. the 3 v operating condition of the adum1250 is examined because it represents the most susceptible mode of operation. the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshold at about 0.5 v, thus establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by = ?= nnrdtdv n ...,2,1;)/( 2 where: is the magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the nth turn in the receiving coil (cm). given the geometry of the receiving coil in the adum1250 and an imposed requirement that the induced voltage is at most 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated, as shown in figure 10 . magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 06401-010 figure 10. maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse (with the worst-case polarity), it reduces the received pulse from > 1.0 v to 0.75 v. note that this is still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the adum1250 transformers. figure 11 expresses these allowable current magnitudes as a function of frequency for selected distances. as shown in figure 11 , the adum1250 is extremely immune and can be affected only by extremely large currents operated at high frequency and very close to the component. for the 1 mhz example, one would have to place a 0.5 ka current 5 mm away from the adum1250 to affect the components operation. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 06401-011 figure 11. maximum allowable current for various current-to-adum1250 spacings note that at combinations of strong magnetic fields and high frequencies, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the threshold of succeeding circuitry. care should be taken in the layout of such traces to avoid this possibility.
adum1250/ADUM1251 rev. 0 | page 12 of 12 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-a a 060506-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 12. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters (inches) ordering guide model number of inputs, v dd1 side number of inputs, v dd2 side maximum data rate (mbps) maximum propagation delay (ns) temperature range package description package option adum1250arz 1 2 2 1 150 ?40c to +105c 8-lead soic_n r-8 adum1250arz-rl7 1 2 2 1 150 ?40c to +105c 8-lead soic_n r-8 ADUM1251arz 1 2 1 1 150 ?40c to +105c 8-lead soic_n r-8 ADUM1251arz-rl7 1 2 1 1 150 ?40c to +105c 8-lead soic_n r-8 1 z = pb-free part. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06113-0-10/06(0)

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